A 28.05Gb/s transceiver using quarter-rate triple-speculation hybrid-DFE receiver with calibrated sampling phases in 32nm CMOS
- Resource Type
- Conference
- Source
- 2017 Symposium on VLSI Circuits VLSI Circuits, 2017 Symposium on. :C326-C327 Jun, 2017
- Subject
Components, Circuits, Devices and Systems Computing and Processing Engineered Materials, Dielectrics and Plasmas Fields, Waves and Electromagnetics Power, Energy and Industry Applications Signal Processing and Analysis Clocks Decision feedback equalizers Latches Transceivers Calibration CMOS technology Monitoring - Language