Topology selection for energy minimization in embedded networks
- Resource Type
- Conference
- Authors
- Dexin Li; Chou, P.H.; Bagherzadeh, N.
- Source
- Proceedings of the ASP-DAC Asia and South Pacific Design Automation Conference, 2003. Design automation conference Design Automation Conference, 2003. Proceedings of the ASP-DAC 2003. Asia and South Pacific. :693-696 2003
- Subject
- Computing and Processing
Communication, Networking and Broadcast Technologies
Components, Circuits, Devices and Systems
Network topology
Embedded system
Network interfaces
Energy efficiency
Firewire
Energy management
Power system management
Power system interconnection
Distributed power generation
Power generation
- Language
The trend towards distributed, networked embedded systems is changing the way power should be managed. Power consumed by bus and network interfaces now matches if not surpasses that of the CPU and is thus becoming a prime candidate for reduction. This paper explores energy-efficient bus topologies as a new technique for global power optimization of embedded systems that are interconnected by high-speed serial network-like buses such as FireWire and a new generation of SoC buses. Our grammar-based representation for these networks enables selection of energy-efficient bus topologies. Experimental results show 15-20% energy saving on the network interfaces without sacrificing system performance.