A 0.5 THz Passive Quadrupler in 65 nm CMOS
- Resource Type
- Conference
- Authors
- Wang, Xin-Yu; Zhang, Jun-Yi; Qie, Jin-Hui; Yang, Fei
- Source
- 2022 IEEE MTT-S International Microwave Workshop Series on Advanced Materials and Processes for RF and THz Applications (IMWS-AMP) Advanced Materials and Processes for RF and THz Applications (IMWS-AMP), 2022 IEEE MTT-S International Microwave Workshop Series on. :1-3 Nov, 2022
- Subject
- Communication, Networking and Broadcast Technologies
Components, Circuits, Devices and Systems
Computing and Processing
Fields, Waves and Electromagnetics
Robotics and Control Systems
Signal Processing and Analysis
Varactors
Radio frequency
Time-frequency analysis
Power demand
Cutoff frequency
Power amplifiers
Bandwidth
terahertz
quadrupler
antisymmetrical varactor
broadband
CMOS
- Language
- ISSN
- 2694-2992
This paper presents a terahertz frequency quadrupler using an accumulation-mode antisymmetrical MOS varactor (ASVAR) for the first time. Frequency multipliers using field-effect transistors (FETs) suffer from poor efficiency above process fT/fmax. Varactor frequency multipliers with a significantly higher dynamic cut-off frequency are better alternatives. While conventional frequency multipliers mostly use III-V devices such as GaAs SBDs, ASVAR's low cost and easy integration with on-chip antennas and drive power amplifiers in the same process make it a better prospect for terahertz applications. The proposed quadrupler reaches a peak output Power of -19.9 dBm at 514 GHz, and a minimum conversion loss of 32.5 dB. The simulated 3-dB output bandwidth is 58 GHz. The quadrupler is designed using 65 nm CMOS process, which does not require DC power consumption.