A Digitized Replica Bitline Delay Technique for Random-Variation-Tolerant Timing Generation of SRAM Sense Amplifiers
- Resource Type
- Periodical
- Authors
- Niki, Y.; Kawasumi, A.; Suzuki, A.; Takeyama, Y.; Hirabayashi, O.; Kushida, K.; Tachibana, F.; Fujimura, Y.; Yabe, T.
- Source
- IEEE Journal of Solid-State Circuits IEEE J. Solid-State Circuits Solid-State Circuits, IEEE Journal of. 46(11):2545-2551 Nov, 2011
- Subject
- Components, Circuits, Devices and Systems
Engineered Materials, Dielectrics and Plasmas
Computing and Processing
Delay
Random access memory
Monte Carlo methods
CMOS technology
CMOS integrated circuits
Threshold voltage
Random variation
replica bitline delay
sense amplifier (SA)
static random access memory (SRAM)
timing generation
- Language
- ISSN
- 0018-9200
1558-173X
A digitized replica bitline delay technique has been proposed for random-variation-tolerant timing generation of static random access memory (SRAM) sense amplifiers (SA). The timing variation of SA attributable to the random variation of transistor threshold voltage $({\rm V}_{\rm TH})$ is reduced by a sufficient count of replica cells, and replica bitline delay is digitized and multiplied to adjust it to the target timing for SA. The variation of the generated timing was 41% smaller than that with a conventional technique and cycle time was reduced 20% at the supply voltage $({\rm V}_{\rm DD})$ of 0.6 V in 40 nm CMOS technology with this scheme.