The 65nm tunneling field effect transistor (TFET) 0.68/spl mu/m/sup 2/ 6T memory cell and multi-V/sub th/ device
- Resource Type
- Conference
- Authors
- Nirschl, T.; Henzler, St.; Fischer, J.; Bargagli-Stoffi, A.; Fulde, M.; Sterkel, M.; Teichmann, P.; Schaper, U.; Einfeld, J.; Linnenbank, C.; Sedlmeir, J.; Weber, C.; Heinrich, R.; Ostermayr, N.; Olbrich, A.; Dobler, B.; Ruderer, E.; Kakoschke, R.; Schrufert, K.; Georgakos, G.; Hansch, W.; Schmitt-Landsiedel, D.
- Source
- Proceedings of 35th European Solid-State Device Research Conference, 2005. ESSDERC 2005. Solid-State Device Research Conference Solid-State Device Research Conference, 2005. ESSDERC 2005. Proceedings of 35th European. :173-176 2005
- Subject
- Components, Circuits, Devices and Systems
Engineered Materials, Dielectrics and Plasmas
Tunneling
FETs
CMOS technology
MOSFET circuits
Doping
Diodes
CMOS process
Leakage current
Logic arrays
System-on-a-chip
- Language
- ISSN
- 1930-8876
2378-6558
The tunneling field effect transistor (TFET) is fabricated using a 65nm standard CMOS process flow. The short-narrow TFET offers an on-current of 550/spl mu/A//spl mu/m which is comparable to the reference MOSFET device. Due to the integrated substrate/well contact the effective area of the TFET is smaller compared to the corresponding MOSFET. Thus, the size of a system-on-a-chip design is reduced by more than 5%. The quantum-mechanical TFET is able to extend the epoch of the CMOS technology by showing reduced short channel effects and smaller leakage currents. A multi-threshold TFET device is proposed which does not need additional implantation steps. A 0.68/spl mu/m/sup 2/ 6 transistor memory cell is fabricated using TFETs and MOSFETs showing the compatibility of MOSFET and TFET and a decrease of the memory array area of approximately 3%.