With the rise of smart wearables came the need for very high processing power built into devices of small area as the size of your wrist. The acronym MicroWIP325 stands for 32-bit Microprocessor Without Interlocked 5 - Pipelines Stages with a Reduced Instruction Set Compiler (RISC). As of April 2017, MIPS32 Release 6 Architecture is existent and several authors have implemented this architectural design and also previous releases of MIPS in Field Programmable Gate Arrays (FPGA) such as Spartan – 03E, Spartan – 6. Through this paper we are focusing on the feasibility of hardware execution within the design space requirements of Xilinx Spartan – 07 (XC7S100-676FGGA-2) FPGA and Intel Cyclone V-E (5CEFA7F31C8N) FPGA, both of which are built using 28nm technology on a comparative study basis for the purpose of marking out design trade-offs between performance and synthesized area. The objective of this paper would be to help researchers and engineers to comprehend on a hardware device perspective with the findings mentioned in this paper in the form of simulations, synthesis and implementation reports generated by Xilinx Vivado and Intel Quartus Prime which includes timing and power analysis of the classical MIPS to realize the superior system for next-generation wearable devices.