Synchronous Ultra-High-Density 2RW Dual-Port 8T-SRAM With Circumvention of Simultaneous Common-Row-Access
- Resource Type
- Periodical
- Authors
- Nii, K.; Tsukamoto, Y.; Yabuuchi, M.; Masuda, Y.; Imaoka, S.; Usui, K.; Ohbayashi, S.; Makino, H.; Shinohara, H.
- Source
- IEEE Journal of Solid-State Circuits IEEE J. Solid-State Circuits Solid-State Circuits, IEEE Journal of. 44(3):977-986 Mar, 2009
- Subject
- Components, Circuits, Devices and Systems
Engineered Materials, Dielectrics and Plasmas
Computing and Processing
Random access memory
Clocks
CMOS technology
Frequency
Multicore processing
Circuit stability
Decoding
Low voltage
System-on-a-chip
SRAM chips
CMOS
dual-port
embedded SRAM
high density
low power
low voltage
memory
65 nm
stability
two-port
variability
- Language
- ISSN
- 0018-9200
1558-173X
We propose an access scheme for a synchronous dual-port (DP) SRAM that minimizes the 8T-DP-cell area and maintains cell stability. A priority row decoder circuit and shifted bitline access scheme eliminates access conflict issues. Using 65 nm CMOS technology (hp90) with the proposed scheme, we fabricated 32 kB DP-SRAM macros. We obtained a 0.71 $\mu\hbox{m}^{2}$ 8T-DP-cell for which the cell size is only 1.44$\times$ larger than a 6T-single-port (SP)-cell. The bit-density of the fabricated 32 kB DP-RAM macro is 667$~$ kbit/mm$^{2}$ , which is 25% larger than a conventional 8T SRAM. The standby leakage is 27% less because of the small drive-NMOS transistor of the proposed 8T-DP-cell.