Digital Calibration of Capacitor Mismatch and Gain Error in Pipelined SAR ADCs
- Resource Type
- Conference
- Authors
- Wang, Yunchuan; Zhang, Li; Mei, Fengyi; Chen, Yongzhen; Wu, Jiangfeng
- Source
- 2021 IEEE 14th International Conference on ASIC (ASICON) ASIC (ASICON), 2021 IEEE 14th International Conference on. :1-4 Oct, 2021
- Subject
- Components, Circuits, Devices and Systems
Heuristic algorithms
Conferences
Capacitors
Switches
Approximation algorithms
Control systems
Calibration
- Language
- ISSN
- 2162-755X
This paper presents a foreground calibration algorithm and a background calibration algorithm for pipelined successive approximation (SAR) analog-to-digital converters (ADC). The foreground calibration for capacitor mismatch is based on injecting the specific sequences to control the switch connection of the capacitor array. And the background calibration is based on the LMS algorithm and Pseudorandom noise (PN) injection to trace the gain of the amplifier. A 14 bit 500 MS/s pipelined SAR ADC is used to verify the effectiveness of the algorithm. The dynamic performance shows SNDR increases from 58.83 dB to 81.92 dB, and the SFDR increases from 64.8 dB to 92.79 dB.