A calibration-free multi-phase sampling Type-II PLL
- Resource Type
- Conference
- Authors
- Xu, Haojie; Jin, Gaofeng; Wu, Jianan; Guo, Huanan; Luo, Xun; Gao, Xiang
- Source
- 2021 IEEE International Conference on Integrated Circuits, Technologies and Applications (ICTA) Integrated Circuits, Technologies and Applications (ICTA), 2021 IEEE International Conference on. :111-112 Nov, 2021
- Subject
- Communication, Networking and Broadcast Technologies
Components, Circuits, Devices and Systems
Robotics and Control Systems
Simulation
Conferences
Circuit simulation
CMOS technology
Calibration
Phase locked loops
System analysis and design
multi-phase sampling PLL
low reference spur
phase margin
- Language
This paper proposes a calibration-free multi-phase sampling Type-II PLL with a lowpass filter based multi-phase error cancellation scheme. The proposed technique enables the simulated reference spur to remain below -79.3dBc even with large multi-phase errors. Moreover, the proposed approach introduces an additional low-frequency right-half-plane zero, which increases the phase margin of the PLL. The design is realized in a 40-nm CMOS technology and verified with circuit simulation.