FPGA Accelerator for Radar-Based Human Activity Recognition
- Resource Type
- Conference
- Authors
- Long, Kangjie; Rao, Chaolin; Zhang, Xiangyu; Ye, Wenbin; Lou, Xin
- Source
- 2022 IEEE 4th International Conference on Artificial Intelligence Circuits and Systems (AICAS) Artificial Intelligence Circuits and Systems (AICAS), 2022 IEEE 4th International Conference on. :391-394 Jun, 2022
- Subject
- Components, Circuits, Devices and Systems
Deep learning
Quantization (signal)
Neural networks
Computer architecture
Logic gates
Energy efficiency
Real-time systems
human activity recognition (HAR)
radar
convolutional neural network (CNN)
edge computing
- Language
Deep learning is enabling radar-based human activity recognition (HAR) to be used in various application scenarios. In many applications, HAR systems need to be implemented in edge devices with the requirement of real-time processing. This paper presents a high-performance and energy efficient FPGA accelerator for radar-based HAR. The accelerator implements the state-of-the-art Mobile RadarNet algorithm to deliver high precision recognition of human activities. Specific architecture with optimized data is proposed to improve the overall computation efficiency. The accelerator is implemented in a field programmable gate array (FPGA)-based system on chip (SoC) platform. Experimental results show that the overall performance in terms of processing speed and energy efficiency is significantly improved without affecting the recognition accuracy.