The Ising machine is a hardware accelerator that finds solutions to combinatorial optimization problems (COPs) using the natural convergence behavior of the Ising model, which comprises artificial-spin network. A previous Ising machine, which is based on the quantum interactions between superconducting quantum bits (qubits) [1], implemented 2048 qubits, but it requires an extremely-low operating temperature (15-20mK) and has significant power consumption (10–1 00kW). Recently, low-power Ising machines [2]–[4] operating at room temperatures have been developed using low-cost CMOS technologies. They implement discrete-time Ising machines using digital [2], [3] or mixed-signal arithmetic circuits [4] to compute the spin operations sequentially. Hence, the performance of these Ising machines is limited by the number of spin-updates, which exponentially increase with the problem size (i.e., the number of binary COP variables). Moreover, the serial nature of the discrete-time Ising machine impedes a fast time-to-solution (TTS) since the connected spins cannot be updated in parallel, which would otherwise lead to oscillations in the spin states. The significant hardware overhead of prior discrete-time Ising machines limits the number of integrated spins feasible. Moreover, integrating bulky random number generators, required for generating randomness for the annealing operations essential for the conventional Ising machines to escape from local minimum solutions, adds hardware overhead.