A fractional-N sub-sampling PLL using a pipelined phase-interpolator with a FoM of −246dB
- Resource Type
- Conference
- Authors
- Narayanan, Aravind Tharayil; Katsuragi, Makihiko; Kimura, Kento; Kondo, Satoshi; Tokgoz, Korkut Kaan; Nakata, Kengo; Deng, Wei; Okada, Kenichi; Matsuzawa, Akira
- Source
- ESSCIRC Conference 2015 - 41st European Solid-State Circuits Conference (ESSCIRC) European Solid-State Circuits Conference (ESSCIRC), ESSCIRC 2015 - 41st. :380-383 Sep, 2015
- Subject
- Communication, Networking and Broadcast Technologies
Components, Circuits, Devices and Systems
Signal Processing and Analysis
Phase locked loops
Jitter
Voltage-controlled oscillators
Phase frequency detector
Phase noise
Dynamic range
Frequency locked loops
- Language
- ISSN
- 1930-8833
This paper presents a fractional-N PLL working in sub-sampling mode using a pipelined phase-interpolator. The proposed pipelined phase-interpolator can achieve high phase linearity with very low power consumption. The fractional-N sub-sampling PLL is implemented in a standard 65nm CMOS technology. The PLL works at a frequency ranging from 4.3GHz to 4.9GHz while consuming 3.3mW. The measured in-band phase noise in fractional-N mode is −114dBc/Hz at 400kHz offset from the carrier, while working with a bandwidth of approximately 2MHz. The combination of high-precision low-power phase-interpolation technique and the sub-sampling technique realizes a high-performance fractional-N frequency synthesizer with the highest reported FoM.