A novel low-leakage power-rail ESD clamp circuit with adjustable triggering voltage and superior false-triggering immunity for nanoscale applications
- Resource Type
- Conference
- Authors
- Lu, Guangyi; Wang, Yuan; Cao, Jian; Jia, Song; Zhang, Xing
- Source
- 2016 IEEE International Symposium on Circuits and Systems (ISCAS) Circuits and Systems (ISCAS), 2016 IEEE International Symposium on. :265-268 May, 2016
- Subject
- Aerospace
Bioengineering
Communication, Networking and Broadcast Technologies
Components, Circuits, Devices and Systems
Signal Processing and Analysis
Electrostatic discharges
Transient analysis
Integrated circuit modeling
Clamps
Simulation
Logic gates
Electrostatic discharge (ESD)
detection circuit
triggering voltage (Vt1)
leakage current (Ileak)
transmission line pulsing (TLP) test
- Language
- ISSN
- 2379-447X
This work presents a novel power-rail electrostatic discharge (ESD) clamp circuit for nanoscale applications. By skillfully incorporating transient and static ESD detection mechanisms into its detection circuit, the proposed circuit achieves a wide range of adjustable triggering voltage (Ft1) while maintaining low standby leakage current (Ileak). Besides, the proposed circuit achieves significantly-improved false-triggering immunity compared with the transient-triggered circuit. All investigated circuits are fabricated in a 65-nm CMOS process. Simulation and test results have both confirmed the superiority of the proposed circuit. In addition, the proposed circuit achieves similar triggering behaviors in both transmission line pulsing (TLP) and very fast TLP (VF-TLP) tests.