SADP etch process development using PR core for sub 17nm DRAM
- Resource Type
- Conference
- Authors
- Xu, Li Tian; Zhang, Shuai; Li, Ling Feng; Liu, Hao; Huang, Xin Wen; Chen, Ying Yi; Su, Xian Wen; Guo, Zhong Ning; Xiu, Chun Yu; Mu, Tian Lei; Lin, Bing Hui; He, Zhong Yi; Zhou, Qing Jun
- Source
- 2022 China Semiconductor Technology International Conference (CSTIC) Semiconductor Technology International Conference (CSTIC), 2022 China. :1-3 Jun, 2022
- Subject
- Bioengineering
Components, Circuits, Devices and Systems
Computing and Processing
Engineered Materials, Dielectrics and Plasmas
Photonics and Electrooptics
Power, Energy and Industry Applications
Signal Processing and Analysis
Silicon compounds
Legged locomotion
Compressive stress
Shape
Lithography
Random access memory
Etching
spacer-defined double patterning
self-aligned double patterning
resist mandrel
resist core
oxide spacer
ALD SiO2
compressive stress
wiggling
leaning
carbon hard mask
buried word line
pitch walking
DRAM
NMC612E
- Language
Self-aligned double patterning (SADP) process has become the standard patterning technology for extending the half-pitch resolution beyond current ArF lithography tool's limit. In this paper, we mitigate the compressive stress of ALD SiO2 spacer in SADP etching and solve the SADP spacer pattern collapse problem to minimize the pitch walking deviation. The SADP technology is applied for 17nm of buried word line (bWL) process to meet DRAM scaling requirements.