Reliability and magnetic immunity of reflow-capable embedded STT-MRAM in 16nm FinFET CMOS process
- Resource Type
- Conference
- Authors
- Chen, Chia-Hsiang; Chang, Chih-Yang; Weng, Chih-Hui; Kuo, Tsung-Han; Wang, Chia-Yu; Shih, Meng-Chun; Chiang, Tien-Wei; Lee, Yuan-Jen; Wang, Roger; Shen, Kuei-Hung; Hung, Arthur; Chuang, Harry
- Source
- 2021 Symposium on VLSI Technology VLSI Technology, 2021 Symposium on. :1-2 Jun, 2021
- Subject
- Bioengineering
Computing and Processing
Photonics and Electrooptics
Power, Energy and Industry Applications
Temperature distribution
Bit error rate
Magnetic noise
Very large scale integration
FinFETs
CMOS process
Reliability
STT-MRAM
reliability
magnetic immunity
- Language
- ISSN
- 2158-9682
We demonstrate the reliability and magnetic immunity of STT-MRAM embedded in 16nm FinFET CMOS process. The technology supports endurance cycles up to 10 5 for wide temperature range from -40°C to 125°C with low bit error rate and passes 10 6 cycles at the worst temperature case of -40°C. Data retention sustains three solder-reflow cycles and up to 10 years with less than 1ppm error rate at 234°C. Read disturb error rate is less than 10 -20 per read. Magnetic immunity of standby and active mode can reach 550Oe for 10 years 1ppm error rate and 800Oe for 0.1ppm error rate per write at 125 °C, respectively.