Reliability and performance optimization of 42V N-channel drift MOS transistor in advanced BCD technology
- Resource Type
- Conference
- Authors
- Molfese, A.; Gattari, P.; Marchesi, G.; Croce, G.; Pizzo, G.; Alagi, F.; Borella, F.
- Source
- 2011 IEEE 23rd International Symposium on Power Semiconductor Devices and ICs Power Semiconductor Devices and ICs (ISPSD), 2011 IEEE 23rd International Symposium on. :340-343 May, 2011
- Subject
- Components, Circuits, Devices and Systems
Computing and Processing
Communication, Networking and Broadcast Technologies
Engineered Materials, Dielectrics and Plasmas
Power, Energy and Industry Applications
Signal Processing and Analysis
Degradation
Stress
Logic gates
Reliability
Buffer layers
Performance evaluation
Optimization
- Language
- ISSN
- 1063-6854
1946-0201
1943-653X
Optimization flow for a 42V N-channel drift MOS in an advanced BCD technology in terms of performance and stability is described. The origin of the very fast on state resistance (R on ) degradation detected during reliability tests under off state on the starting device has been identified in borderless silicon nitride used as stop layer during contact etch. The final solution including a process step introduction, device geometry modification and drain doping profile optimization improves performance and addresses both voltage capability and reliability requirements.