LHC Clock Conditioning Circuit for AFP Trigger Module
- Resource Type
- Conference
- Authors
- Georgiev, Vjaceslav; Zich, Jan
- Source
- 2020 International Conference on Applied Electronics (AE) Applied Electronics (AE), 2020 International Conference on. :1-4 Sep, 2020
- Subject
- Components, Circuits, Devices and Systems
Computing and Processing
Power, Energy and Industry Applications
Signal Processing and Analysis
Delays
Temperature measurement
Temperature sensors
Large Hadron Collider
Clocks
Integrated circuits
Field programmable gate arrays
CERN
delay lines
high energy physics
LHC
particle accelerator
clock conditioning
physical instrumentation
synchronization
rad-hard
- Language
- ISSN
- 1803-7232
1805-9597
The timing and synchronisation of the detectors in particle physics play the key role due to the high event rates at particle accelerators. The trigger module in ATLAS Forward Physics project selects the events from time of flight detector belonging to the proton bunch. As the time position of the proton bunch is the same within each Large Hadron Collider period, from the clock conditioning circuit (CCC) can be derived the qualification signal for the trigger module input signals. The further processing of these events in trigger module is allowed by the CCC qualification. High speed delay line integrated circuits together with the logic gates and FPGA based controller were used for the realization of the CCC. This paper describes the design, construction and test procedure of the CCC.