A 6Bit 3GS/s two-channel time interleaved interpolating flash ADC
- Resource Type
- Conference
- Authors
- YI-Cheng Chen; Jyun-Syong Lai; Zhi-Ming Lin
- Source
- 2013 IEEE International Conference of Electron Devices and Solid-state Circuits Electron Devices and Solid-State Circuits (EDSSC), 2013 IEEE International Conference of. :1-4 Jun, 2013
- Subject
- Components, Circuits, Devices and Systems
ISO standards
Time-frequency analysis
Interpolation
flash adc
comparator
analog-to-digital converter (ADC)
- Language
In this paper a 6-bit two-channel time interleaved interpolating flash analog-to-digital converter (ADC) is designed in TSMC 0.18-µm CMOS process. This circuit consists of mainly a sample-and-hold circuit, a set of single-transistor comparators with interpolating circuit, and a thermometer code to binary code encoder. By interpolating the double channel time-interleaved architecture, we reduced a lot of comparators and increased the speed. The simulation results show that the circuit obtained +0.24/−0.23 LSB differential non-linearity error (DNL) and +0.24/−0.35 LSB integral non-linearity (INL). The simulated speed is 3GS/s. The total power dissipation is 0.73 mW at 1.5V power supply.