True random number generators(TRNGs) are essential in hardware-security-related applications including data encryption, initialization parameters, key generation, authentication protocol, to name a few. Recent years have witnessed a number of custom-IC-based TRNG designs presented in literatures [1-6]. Metastability in cross coupled inverters, comparators and SRAMs can be adopted to generate truly random numbers with high throughput [1], [2], nevertheless, a complex post-processing unit is needed to remove the process-variation caused systematic bias, resulting in a large silicon area of 2254µm2 using a 28-nm CMOS process (i.e., 2875KF2) [1]. In [3], chaotic-map based TRNG can provide high-quality random bits, however, it needs a relatively-tedious post-processing step, leading to significantly reduced throughput of 0.27Mbps and increased silicon area of 210Kµm2 (including ADC). In [4], jitter noise of SRAM's bitline is used to realize an in-memory TRNG, while its energy consumption is as high as 15.13pJ/bit at a relatively low throughput of 4.5Mbps. In [5], [6], random clock jitter of ring oscillators (ROs) is exploited to construct high performance TRNGs. The drawback of [5] is the needed large silicon area of 4335µm 2 using a 40-nm CMOS process, which is largely attributed to the complex feedback structure and the post-processing unit. The RO-based edge-chasing TRNG in [6] suffers from low energy efficiency of 27.28pJ/bit, which is not suitable for the energy-constrained applications.