A high-speed CRC-32 Implementation on FPGA
- Resource Type
- Conference
- Authors
- Cai, Fangfei; Nie, Yuchen; Zhang, Keran; Luo, Hangzai; Li, Yanyan
- Source
- 2024 4th International Conference on Neural Networks, Information and Communication (NNICE) Neural Networks, Information and Communication (NNICE), 2024 4th International Conference on. :1665-1668 Jan, 2024
- Subject
- Communication, Networking and Broadcast Technologies
Components, Circuits, Devices and Systems
Computing and Processing
Robotics and Control Systems
Signal Processing and Analysis
Cyclic redundancy check
Scalability
Design methodology
Artificial neural networks
Throughput
Table lookup
Resource management
CRC
Lookup table
FPGA
- Language
Cyclic Redundancy Check (CRC) is widely used for transmission error detection in various communication interfaces. As the transmission rate increases, accelerating CRC with lower resource consumption for high-speed interfaces becomes significant. This paper analyzes and implements a typical CRC algorithm (Stride-x) and designs a padding-zero strategy to support the input data length with multiples of byte. Besides, experiments are conducted to validate the proposed algorithm on Xilinx FPGA platforms. When stride is 1, the proposed algorithm outperforms a typical parallel CRC algorithm in throughput and resource consumption with various input bus widths (32/128/256 bits).