A Reconfigurable 1T1C eDRAM-based Spiking Neural Network Computing-In-Memory Processor for High System-Level Efficiency
- Resource Type
- Conference
- Authors
- Kim, Seryeong; Kim, Soyeon; Um, Soyeon; Kim, Sangjin; Li, Zhiyong; Kim, Sanyeob; Jo, Wooyoung; Yoo, Hoi-jun
- Source
- 2023 IEEE International Symposium on Circuits and Systems (ISCAS) Circuits and Systems (ISCAS), 2023 IEEE International Symposium on. :1-5 May, 2023
- Subject
- Components, Circuits, Devices and Systems
Power, Energy and Industry Applications
Signal Processing and Analysis
Charge pumps
Circuits and systems
Microprocessors
Neurons
Memory management
Energy efficiency
Common Information Model (computing)
Computing-In-Memory
1T1C memory
eDRAM CIM
spiking neural network
system efficiency
reconfigurable
- Language
- ISSN
- 2158-1525
Spiking Neural Network (SNN) Computing-In-Memory (CIM) was proposed for high macro-level energy efficiency. However, system-level energy efficiency is limited by EMA due to a large intermediate activation footprint requirement. To reduce the EMA, a large capacity SNN CIM is needed to load tons of weights in the CIM. This paper proposes a high-density 1T1C eDRAM-based SNN CIM processor for supporting high system-level energy efficiency with two key features: 1) High-density and low-power Reconfigurable Neuro-Cell Array (ReNCA) for memory and SNN peripheral logic using a charge pump and reusing 1T1C cell array, achieving 41% area and 90% power reduction compared to previous work. 2) Reconfigurable CIM architecture with dual-mode ReNCA and Dynamic Adjustable Neuron Link (DAN Link) for layer fusion increases system-level efficiency including intermediate and weight EMA. It achieves $10\times$ higher state-of-the-art system-level energy efficiency including EMA.