This paper introduces a new digital baseband processor for UHF tags, which is a low-power digital circuit. Based on ISO/IEC18000-6C protocol, this design establishes the system architecture of the reader and focuses on the key technologies of the digital baseband in the physical layer of the reader as follows: the high-speed processing capability of the on-board ZYNQ is utilized to implement the transmit link design of the reader, encompassing the data encoding, group framing, clock management, random number generator and cyclic redundancy checksum. VIVADO is employed to simulate the communication between the tag and the reader, and the simulation results meet the design requirements.