As a highly repetitive logic operation unit in programmable logic modules, the operating speed of a carry adder circuit is crucial to the overall performance of the programmable logic circuit. In order to optimize circuit propagation delay and area overhead, this paper proposes an improved design scheme for carry adder circuits. Firstly, several basic adder structure types and their performance characteristics are compared to determine the most suitable architecture for carry adder circuits in programmable modules. Then, based on the carry-propagate principle of the carry lookahead adder, a novel single MOS transmission gate structure is proposed to optimize the underlying carry logic circuit. Finally, the carry adder circuit is implemented using a full-custom design flow in TSMC 28nm technology. Experimental results show that compared to existing logic designs, the proposed carry adder circuit in this paper reduces propagation delay and area overhead by 14% and 26.5% respectively.