As the prevailing copper interconnect technology advances to its fundamental physical limit, interconnect delay due to ever-increasing wire resistivity shows a significant impact on circuit performance. Bundled single-wall carbon nanotubes (SWCNTs) interconnects have emerged as a promising candidate technique to replace copper interconnects thanks to their superior conductivity and immunity to electromigration. To deliver satisfying performance within low power consumption, the CNT interconnect timing is optimized by adjusting either the interconnect geometry, e.g., CNT diameter and nanotube pitch, or the buffer insertion. These two operations are normally optimized separately, which leads to an inferior design that is not global optimum. To resolve this problem, we first propose a model that parameterizes SWCNT interconnects. We then leverage the known Bayesian optimization to optimize SWCNT global interconnect and buffer insertion simultaneously to promote interconnect performance. The proposed method is assessed based on a set of interconnect benchmarks at 22nm technology node. Compared to the state-of-the-art methods, the Bayesian co-optimization technique can reduce more than 17% power delay product (PDP). Additionally, we evaluate the SWCNT interconnect performance at 32nm, 22nm and 16nm technology nodes. Compared to the SOTA method with the same wire dimension, SWCNT interconnects optimized by the proposed method can further reduce delay and PDP relative to copper by 35% and 45% on average, which highlights the promising prospect of the SWCNT interconnect technology and the effectiveness of our proposed technique.