This paper presents the FPGA implementation results of the LMS algorithm with complex input/output data. The implementation is fulfilled based on Xilinx system generator in a graphical programming manner, and demonstrated on Xilinx KC705 evaluation board. It is shown that complex LMS algorithm, regardless of the order of filter, can support more than 200 million-samples-per-second (Msps) throughput rate when 16-bit complex input/output data are considered, with latency of 3 or 4 clock periods (i.e. 15ns or 20ns when clock frequency is 200MHz).