This paper introduces a 14-bit 150KS/s successive approximation register (SAR) analog-to-digital converter (ADC) with programmable gain amplifier (PGA) used in CMOS Image Sensor (CIS), which doesn't adopt calibration module as well. The pixel size is 12.5 um × 12.5 um and the pixel array of mentioned CIS is 1026 × 1024. In order to realize the goal of converting more pixel signal, three-way PGA works at the same time to sample three columns of pixel signal and then sends the amplified signal into SAR ADC step by step. What's more, multiple reference voltages and complementary capacitor array are used to reduce the capacitor number and improve resolution, accepting 4.8 V pp differential input signal. The prototype circuit is fabricated in 180 nm 3.3-V CMOS process. The total area of chip is 26.25 × 18.38 mm 2 . At a 3.3-V supply and 150 KS/s sampling rate, the ADC with PGA achieves SNR of 71.72 dB and SFDR of 82.91 dB while the single ADC consumes 477.2 uW.