The relationship between low resistance $(R_{\rm on})$ and cell size (from 40 nm to 100 $\mu\hbox{m}$) is systematically investigated using a 1-Mb $\hbox{Cu}_{x}\hbox{Si}_{y}\hbox{O}$ resistive RAM (RRAM) array. To our knowledge, this is the first study to attempt such an endeavor. Spacer pattern technology is employed to obtain a small cell size on the basis of a 0.13-$\mu \hbox{m}$ standard logic process. $R_{\rm on}$ exhibits minimal change at 100 $\mu\hbox{m}$ to 90 nm of RRAM size. However, it quadratically increases at 90 to 40 nm. The reset current, which is highly dependent on $R_{\rm on}$, is linearly reduced fivefold in accordance with cell size, thereby improving overall power reduction and cell size scaling. The $R_{\rm on}$ dependence on cell size can be well explained by the dendritelike conductive filament model.