Synthesis support for design partitioning
- Resource Type
- Conference
- Authors
- Willoughby, J.
- Source
- Proceedings of Meeting on Verilog HDL (IVC/VIUF'97) Verilog HDL Verilog HDL Conference, 1997., IEEE International. :32-37 1997
- Subject
- Computing and Processing
Circuit synthesis
Runtime
Boundary conditions
Logic design
Pins
Design engineering
Timing
Automatic logic units
Automatic control
Strain control
- Language
As designs become larger and larger it becomes necessary to partition the design, not only to meet synthesis tool restrictions, but also to perform parallel design processing by multiple engineers and/or on multiple machines. Partitioning requires the assignment of timing and loading budgets across module boundaries. This is an inefficient and time-consuming task if performed by hand. Logic synthesis tools can utilize techniques of constraint propagation combined with hierarchical controls to perform this task automatically. This approach will result in improved results and shorter design times.