This article reports a high voltage PLDMOS with 25V operating voltage and 40V breakdown voltage. Usually the PLDMOS adopts N-well as channel, and the N-well is as the drift region of NLDMOS. The PLDMOS presented in this paper adopts N-type EPI as channel, which is not affected by NLDMOS drift region. The low doping concentration of N-type EPI causes the punch through (punch through for short) in PLDMOS between the source and drain when the channel length is short than 2.5um. The PLDMOS in this paper adopts blanket phosphorus implant to suppress punch through between source and drain, and blanket boron implant to adjust threshold voltage. Without adding mask, the resulting device still has excellent characteristics under short channel length.