Efficient protection of the pipeline core for safety-critical processor-based systems
- Resource Type
- Conference
- Authors
- Touloupis, E.; Flint, J.A.; Chouliaras, V.A.; Ward, D.D.
- Source
- IEEE Workshop on Signal Processing Systems Design and Implementation, 2005. Signal Processing Systems Signal Processing Systems Design and Implementation, 2005. IEEE Workshop on. :188-192 2005
- Subject
- Signal Processing and Analysis
Computing and Processing
Communication, Networking and Broadcast Technologies
Protection
Pipelines
Circuit faults
Computer errors
Clocks
CMOS process
Circuit synthesis
Redundancy
Control systems
Fault tolerant systems
- Language
- ISSN
- 2162-3562
2162-3570
The increasing number of safety-critical commercial applications has generated a need for components with high levels of reliability. As CMOS process sizes continue to shrink, the reliability of ICs is negatively affected since they become more sensitive to transient faults. New circuit designs must take this fact into consideration, and incorporate adequate protection against the effects of transient faults. This paper presents a novel method for protecting the pipelined execution unit of an embedded processor. It is based on a self-configured architecture with hybrid redundancy that can mask single and multiple errors, which can occur on storage elements due to transient or permanent faults. This concept can be easily applied to any processing architecture of this nature with a high safety integrity level. Results from error-injection experiments are also reported that show that this design can maintain a non-interrupted and failure-free operation under single and double errors with a probability that exceeds 99.4%.