Fault tolerant design for cascaded H-bridge multi-level converter based electronic power transformer
- Resource Type
- Conference
- Authors
- Sang, Zi-xia; Huang, Jia-qi; Du, Zhi; Zhou, Si-xuan; Yan, Jiong; Xu, Qiu-shi; Lei, He; Wang, Si-cong
- Source
- 2018 13th IEEE Conference on Industrial Electronics and Applications (ICIEA) Industrial Electronics and Applications (ICIEA), 2018 13th IEEE Conference on. :2280-2284 May, 2018
- Subject
- Communication, Networking and Broadcast Technologies
Components, Circuits, Devices and Systems
Computing and Processing
Fields, Waves and Electromagnetics
Photonics and Electrooptics
Power, Energy and Industry Applications
Robotics and Control Systems
Signal Processing and Analysis
Transportation
Circuit faults
Fault tolerant systems
Redundancy
Voltage control
Insulated gate bipolar transistors
electronic power transformer (EPT)
redundancy
fault tolerant strategy
cascaded multi-level converter (CMLC)
- Language
- ISSN
- 2158-2297
As a prospective electric component in the power grid, the reliability of electronic power transformer (EPT) affects the security of the power grid. The fault tolerant strategy about the redundancy control can improve the reliability of EPT, hence secure the power grid. This paper presents the design of fault tolerant strategy on a cascaded multi-level converter (CMLC) based EPT. The operational principle and control scheme for the redundancy control are introduced and analyzed. The proposed fault tolerant strategies are implemented on a single phase nine-level CMLC based EPT in Saber simulation platform. Simulation is illustrated to verify the performance of the proposed fault tolerant design with redundancy control.