Design-Technology Co-optimization (DTCO) for Emerging Disruptive Logic & Embedded Memory Process Technologies
- Resource Type
- Conference
- Authors
- Niu, Jessie Xuhua; Veluri, Hasita; Thean, Aaron Voon-Yew
- Source
- 2019 Electron Devices Technology and Manufacturing Conference (EDTM) Electron Devices Technology and Manufacturing Conference (EDTM), 2019. :246-248 Mar, 2019
- Subject
- Bioengineering
Communication, Networking and Broadcast Technologies
Components, Circuits, Devices and Systems
Computing and Processing
Engineered Materials, Dielectrics and Plasmas
Engineering Profession
Photonics and Electrooptics
Power, Energy and Industry Applications
Logic gates
Random access memory
Computer architecture
Thin film transistors
Microprocessors
- Language
In this paper, we discuss the DTCO of two disruptive emerging device technologies; Vertical gate-all-around FETs and embedded monolithic 3D (ITIR) integration of 2D material-based resistive RAM and switch transistors. We showed that VFET has the potential for lower parasitics and improved SRAM performance. In the case of the 2D material-based ITIR, we show that stacking of nanosheets and reduction of set current is necessary to scale the cell below 0.1$\mu m^{2}$ cell sizes.