ALMP: a shifting memory architecture for loop pipelining
- Resource Type
- Conference
- Authors
- Ugurdag, H.F.; Papachristou, C.A.
- Source
- Proceedings 1992 IEEE International Conference on Computer Design: VLSI in Computers & Processors Computer Design: VLSI in Computers and Processors, 1992. ICCD '92. Proceedings, IEEE 1992 International Conference on. :564-568 1992
- Subject
- Computing and Processing
Communication, Networking and Broadcast Technologies
Components, Circuits, Devices and Systems
Photonics and Electrooptics
Signal Processing and Analysis
Memory architecture
Pipeline processing
Assembly
Job shop scheduling
Processor scheduling
Belts
Hardware
Delay
Multiprocessor interconnection networks
Physics
- Language
A multiprocessor architecture called ALMP, which specifically suits loop pipelining, is proposed. The processors in ALMP work like machines in an assembly line in a plant. An assembly line scheduling method (ALMap) has also been developed. ALMP enables processors to communicate with each other through memory modules that shift from processor to processor as if they are on a conveyor belt. The scheduling method is briefly described, and architectural issues are examined.ETX