Double-Via-Driven Standard Cell Library Design
- Resource Type
- Conference
- Authors
- Lin, Tsai-Ying; Lin, Tsung-Han; Tung, Hui-Hsiang; Lin, Rung-Bin
- Source
- 2007 Design, Automation & Test in Europe Conference & Exhibition Design, Automation & Test in Europe Conference & Exhibition, 2007. DATE '07. :1-6 Apr, 2007
- Subject
- Computing and Processing
Communication, Networking and Broadcast Technologies
Components, Circuits, Devices and Systems
Libraries
Routing
Wires
Pins
Costs
Computer science
Design engineering
Computer aided manufacturing
Standards development
Bipartite graph
- Language
- ISSN
- 1530-1591
1558-1101
Double-via placement is important for increasing chip manufacturing yield. Commercial tools and recent work have done a great job for it. However, they are found with a limited capability of placing more double vias (called via1) between metal 1 and metal 2. Such a limitation is caused by the way we design the standard cells and can not be resolved by developing better tools. This paper presents a double-via-driven standard cell library design approach to solving this problem. Compared to the results obtained using a commercial cell library, our library on average achieves 78% reduction in dead vias and 95% reduction in dead via1s at the expense of 11% increase in total via count. We achieve these results (almost) at no extra cost in total cell area and wire length.