Improvement of short-channel characteristics of a 0.1-μm PMOSFET with ultralow-temperature nitride spacer by using a novel oxide capped boron uphill treatment
- Resource Type
- Periodical
- Authors
- Yang, C.W.; Fang, Y.K.; Chen, C.H.; Wang, W.D.; Ting, S.F.; Chen, S.F.; Cheng, J.Y.; Wang, M.F.; Chen, C.L.; Yao, L.G.; Lee, T.L.; Chen, S.C.; Yu, C.H.; Liang, M.S.
- Source
- IEEE Electron Device Letters IEEE Electron Device Lett. Electron Device Letters, IEEE. 24(1):43-45 Jan, 2003
- Subject
- Engineered Materials, Dielectrics and Plasmas
Components, Circuits, Devices and Systems
MOSFET circuits
Boron
Annealing
CMOS technology
Plasma temperature
Ion implantation
Silicon
Very large scale integration
Laboratories
- Language
- ISSN
- 0741-3106
1558-0563
The thermal annealing at 720/spl deg/C for 2 hr (called boron uphill treatment) with an SiO 2 -capped layer was applied after source/drain extensions (SDE) implantation to improve the short channel characteristics of a 0.1-μm PMOSFET with an ultra-low temperature nitride spacer. The influence and the mechanism of the capped layer on this uphill treatment were investigated. The results show that the capped layer treatment indeed leads to a shallower junction, improved V/sub th/ roll-off characteristic, and added immunity against subsurface punchthrough.