The channel count of implantable neural interfaces has grown rapidly as brain-machine interface applications emerge from basic brain disorder monitoring, motor control, to voice reconstruction. However, limited on-implant power and area budget hinder the development of neural interfaces and multi-channel integration. As shown in Fig. 1, Although time-division multiplexing (TDM) before ADC [1], [2] alleviates the area consumption over architecture without TDM [3], the recording front-end still occupies large on-chip area, resulting average channel area of over $0.01 \text{mm}^{2}$. Recently, TDM over the entire readout circuits has been adopted to reduce area consumption per channel [4], [5]. However, they induce extra overhead to resolve DC offset variations between channels. More importantly, the power consumption issue associated with large volumes of neural signal transmission remains unsolved.