Chip package interaction with Cu Pillar interconnects - systematic study of key factors impacting the qualification
- Resource Type
- Conference
- Authors
- Boehme, Bjoern; Breuer, Dirk; Goetze, Christian; Estoque, Al Rhea; Tischer, Falk; Kuechenmeister, Frank; Paul, Jens; Thiele, Michael
- Source
- 2017 IMAPS Nordic Conference on Microelectronics Packaging (NordPac) Microelectronics Packaging (NordPac), 2017 IMAPS Nordic Conference on. :68-73 Jun, 2017
- Subject
- Components, Circuits, Devices and Systems
Computing and Processing
Engineered Materials, Dielectrics and Plasmas
Fields, Waves and Electromagnetics
Photonics and Electrooptics
Metals
Stress
Qualifications
Packaging
Routing
Substrates
Silicon
CPI
BEOL
Metal density
- Language
Advanced silicon technology nodes are using backend of line (BEOL) stacks consisting of ultra low-k (ULK) materials. ULK materials in combination with Flip Chip (FC) packages and Cu pillar first level interconnects require a chip package interaction (CPI) characterization strategy. Package level tests are needed to account for the thermal mismatch or warpage induced stress between the silicon die and the polymer substrate.