A high-performance re-configurable Convolutional Neural Network (CNN) accelerator with multiple modes is introduced in this paper. The conventional CNN involves extensive computations, but this paper presents the Multiple Modes CNN Computation Unit (MMCN), which, in comparison, accomplishes the convolution model without including pooling and dense layers. As presented in this paper, the pooling layer has been replaced with a pooling unit comprising several logic gates, reducing the MMCN’s area. Due to the modifications detailed in this paper, the computational path of MMCN is considerably shorter than that of a conventional CNN chip. Therefore, this paper aims to reduce the computation circuit compared to conventional CNN accelerators. Owing to the modifications detailed in this paper, the computational path of MMCN is considerably shorter than that of a conventional CNN chip. The proposed MMCN significantly reduces the circuit area by eliminating redundant circuit components. Finally, the proposed MMCN is evaluated using the VGG-16 model and the CIFAR-10 dataset, with implementation in the TSMC 90-nm CMOS process. This implementation results in an 89% reduction in power consumption, 70% reduction in area, and 62.8% increase in speed, with only 1% accuracy loss.