Inter-Temperature Bandwidth Reduction in Cryogenic QAOA Machines
- Resource Type
- Periodical
- Authors
- Ueno, Y.; Tomida, Y.; Tanimoto, T.; Tanaka, M.; Tabuchi, Y.; Inoue, K.; Nakamura, H.
- Source
- IEEE Computer Architecture Letters IEEE Comput. Arch. Lett. Computer Architecture Letters. 23(1):9-12 Jan, 2024
- Subject
- Computing and Processing
Bandwidth
Qubit
Logic gates
Quantum computing
Computer architecture
Superconducting cables
Cryogenics
cryogenic electronics
quantum computing
qubit
superconducting logic circuits
- Language
- ISSN
- 1556-6056
1556-6064
2473-2575
The bandwidth limit between cryogenic and room-temperature environments is a critical bottleneck in superconducting noisy intermediate-scale quantum computers. This paper presents the first trial of algorithm-aware system-level optimization to solve this issue by targeting the quantum approximate optimization algorithm. Our counter-based cryogenic architecture using single-flux quantum logic shows exponential bandwidth reduction and decreases heat inflow and peripheral power consumption of inter-temperature cables, which contributes to the scalability of superconducting quantum computers.