With the increases of design complexity in FPGA, a tough assignment of the verification is obvious. Modular design method is come up to maximize synergy and to reduce duplication, and Verification IP(VIP) is the same way. In order to improve efficiency at work and ensure the requirements of product quality, a validation automation method for simulation based on reconfigurable VIP cells was proposed and FAS tool was developed [1] . This paper presents an inspection of the tool, and the testcases set on the verification of controller area network (CAN) bus controller are designed, and the application results of Verification for serial CAN bus show that the design play an important role in reducing the complexity of verification environment setup and enhancing the synchronization of verification documents, models and environment code, lowering the risks of running behind schedule and meets the requirements of high quality standards.