An all-digital delay-locked loop for high-speed memory interface applications
- Resource Type
- Conference
- Authors
- Chen, Shih-Lun; Ho, Ming-Jing; Sun, Yu-Ming; Lin, Maung Wai; Lai, Jung-Chin
- Source
- Technical Papers of 2014 International Symposium on VLSI Design, Automation and Test VLSI Design, Automation and Test (VLSI-DAT), 2014 International Symposium on. :1-4 Apr, 2014
- Subject
- Components, Circuits, Devices and Systems
Computing and Processing
Signal Processing and Analysis
Delays
Delay lines
Tuning
Inverters
Jitter
CMOS process
System-on-chip
all-digital delay-locked loop (ADDLL)
delay-locked loop (DLL)
coarse delay line (CDL)
fine delay line (FDL)
double data rate (DDR)
system-on-a-chip(SoC)
- Language
This paper presents an all-digital delay-locked loop with the novel digital delay line for high-speed memory interface applications. The proposed digital delay line has smaller tuning step and better tuning linearity than the prior arts. The proposed ADDLL inside the DDR3 PHY for the purpose of the 90-degree phase shift and read leveling is fabricated in a 40nm low-power CMOS process. The testchip is successfully verified at the data rate of 800∼1600Mbps. The measured peak-to-peak and rms jitter of the write DQS are 60ps and 10ps at the data rate of 1600Mbps, respectively.