RF passive device modeling and characterization in 65nm CMOS technology
- Resource Type
- Conference
- Authors
- Lourandakis, Errikos; Stefanou, Stefanos; Nikellis, Konstantinos; Bantas, Sotiris
- Source
- International Symposium on Quality Electronic Design (ISQED) Quality Electronic Design (ISQED), 2013 14th International Symposium on. :658-664 Mar, 2013
- Subject
- Components, Circuits, Devices and Systems
Engineered Materials, Dielectrics and Plasmas
Computing and Processing
Conductors
Capacitance
Metals
Microstrip
Semiconductor device modeling
Semiconductor process modeling
Integrated circuit modeling
CMOS integrated circuits
inductors
capacitors
- Language
- ISSN
- 1948-3287
Rapid passive device modeling is discussed in this work based on test structures fabricated in a 65nm CMOS process with M1–M9 copper metal layers and one aluminum metal layer AP. Capacitance extraction for overlapping microstrips and shielded microstrip structures is investigated. Individual capacitances are modeled in terms of area and fringe components, either between microstrips or between microstrips and silicon substrate. Good correlation to silicon data is achieved for the fabricated test structures. The validity of the proposed model is also investigated for complex passive devices such as inductors and interdigitated capacitors. Device metrics for both types of passive devices are investigated and compared to measured silicon data. Good agreement is achieved in all cases proving the accuracy of the proposed modeling approach.