A statistical study of the effectiveness of BIST jitter measurement techniques
- Resource Type
- Conference
- Authors
- Bordoley, D.; Nguyen, H.; Soma, M.
- Source
- ICCAD-2005. IEEE/ACM International Conference on Computer-Aided Design, 2005. Computer Aided Design Computer-Aided Design, 2005. ICCAD-2005. IEEE/ACM International Conference on. :100-107 2005
- Subject
- Computing and Processing
Components, Circuits, Devices and Systems
Robotics and Control Systems
Built-in self-test
Jitter
Measurement techniques
Clocks
System performance
Time measurement
Phase locked loops
Frequency measurement
System testing
Gaussian distribution
- Language
- ISSN
- 1092-3152
1558-2434
This paper describes a statistical study of the effectiveness of state-of-the-art built-in-self-test (BIST) jitter measurement techniques. Many BIST solutions under-sample the signal under test, estimating the jitter in a system based upon a subset of the total number of clock edges. In this paper, we explore how under-sampling affects the accuracy of jitter measurements, and demonstrate a technique for estimating the actual jitter using a Gaussian distribution estimation. Our theoretical results were verified through a simulation study and comparison to experimental data collected from a 400 MHz phase-locked loop supplied by an industry sponsor.