A 3nm Ultra High-Speed (4.5GHz) SRAM Cache Design With Wide DVFS Range
- Resource Type
- Conference
- Authors
- Sinha, Sandipan; Trivedi, Manish; Singh, Jaswinder; Enjapuri, Sriharsha; Gujjar, Deepesh; Halli, Ramesh; Gurumurthy, Girishankar
- Source
- 2024 37th International Conference on VLSI Design and 2024 23rd International Conference on Embedded Systems (VLSID) VLSID VLSI Design and 2024 23rd International Conference on Embedded Systems (VLSID), 2024 37th International Conference on. :84-89 Jan, 2024
- Subject
- Communication, Networking and Broadcast Technologies
Components, Circuits, Devices and Systems
Computing and Processing
Power, Energy and Industry Applications
Robotics and Control Systems
Signal Processing and Analysis
Technological innovation
Embedded systems
Random access memory
Voltage
Bandwidth
High-voltage techniques
Very large scale integration
SRAM
writability
standby-power
access time
high speed cache
low voltage robustness
write time
- Language
- ISSN
- 2380-6923
The paper presents SRAM cache design in 3nm FinFET technology for L1 cache applications achieving 4.5GHz frequency and demonstrates circuit techniques to enable wide-range DVFS (Dynamic Voltage and Frequency scaling) operation. The paper proposes an innovative write circuitry to address the writability concerns at ultra-low-voltages (0.45v) as well as eliminating performance limitation of the traditional write-circuit at high voltage (1.1v). To reduce clock input pin cap and standby power, internal clock generation circuit is proposed. The paper introduces the concept of Dynamic Delay-Select (DELSEL), which helps to boost frequency at performance-intensive voltage corners. The techniques mentioned are implemented in a 3nm FinFET SRAM.