Improving gate oxide integrity in p/sup +/pMOSFET by using large grain size polysilicon gate
- Resource Type
- Conference
- Authors
- Koda, M.; Shida, Y.; Kawaguchi, J.; Kaneko, Y.
- Source
- Proceedings of IEEE International Electron Devices Meeting Electron devices Electron Devices Meeting, 1993. IEDM '93. Technical Digest., International. :471-474 1993
- Subject
- Components, Circuits, Devices and Systems
Engineered Materials, Dielectrics and Plasmas
Photonics and Electrooptics
MOSFET circuits
Grain size
Boron
Large scale integration
Electric breakdown
Semiconductor films
MOS capacitors
Annealing
Size control
Silicon
- Language
- ISSN
- 0163-1918
The effect of polysilicon grain size on the gate oxide integrity in p/sup +/pMOS devices was investigated by measuring the electrical characteristics of a MOS capacitor. Good gate oxide integrity was never obtained when using conventional polysilicon with a small (/spl sim/0.05 /spl mu/m) grain size. We report for the first time use of large (/spl sim/1.0 /spl mu/m) grain size polysilicon to solve this problem for gate oxide quality. Additionally, in large-grain-size polysilicon, the efficiency of boron activation was increased and boron diffusion through the gate oxide into the channel region was strongly suppressed.ETX