Optimization of Tungsten Plug Thin Film Process to Improve the Fill Seam and Contact Resistance in 180nm CMOS Technology
- Resource Type
- Conference
- Authors
- Chauhan, A.K.; Teja, V.S.; Chawla, P.; Sharma, A.K.; Attri, R.; Gupta, M.; Singh, M.K.; Wadhwa, M.
- Source
- 2024 8th IEEE Electron Devices Technology & Manufacturing Conference (EDTM) Electron Devices Technology & Manufacturing Conference (EDTM), 2024 8th IEEE. :1-3 Mar, 2024
- Subject
- Bioengineering
Components, Circuits, Devices and Systems
Computing and Processing
Engineered Materials, Dielectrics and Plasmas
Engineering Profession
Fields, Waves and Electromagnetics
General Topics for Engineers
Photonics and Electrooptics
Tungsten
Production
Contact resistance
CMOS technology
Manufacturing
Electrical resistance measurement
Standards
thin film
W plug
aspect ratio
step-coverage
Seam
CMP
metal CVD
contact resistance
X-SEM
- Language
In this manuscript, an experimental study to optimize the tungsten (W) deposition process was carried out to address the poor fill seam issue and to improve the contact resistance in CMOS 180nm technology. A modified tungsten deposition recipe was introduced in both contact and via modules, wherein; three-step process was adopted in place of two steps. Tungsten nucleation and fill process parameters were optimized to attain better seam and step coverage. In modified recipe, an improvement of 17.4% and 16% was measured in step coverage and contact resistance respectively.