Susceptibility of planar and 3D tri-gate technologies to muon-induced single event upsets
- Resource Type
- Conference
- Authors
- Seifert, Norbert; Jahinuzzaman, Shah; Velamala, Jyothi; Patel, Nikunj
- Source
- 2015 IEEE International Reliability Physics Symposium Reliability Physics Symposium (IRPS), 2015 IEEE International. :2C.1.1-2C.1.6 Apr, 2015
- Subject
- Components, Circuits, Devices and Systems
Engineered Materials, Dielectrics and Plasmas
Power, Energy and Industry Applications
Mesons
Neutrons
Particle beams
Life estimation
Random access memory
Acceleration
Atmospheric modeling
single event upset
muon
accelerated testing
planar
Tri-Gate CMOS
- Language
- ISSN
- 1541-7026
1938-1891
We report on muon-induced single event upsets (SEU) in SRAMs built on 32nm planar and 22nm and 14nm 3D Tri-Gate technologies. Experimental cross sections were measured using the M20C positive muon beamline at TRIUMF. Physics-based simulations were conducted to estimate sea-level SEU rates for both, positive and negative muons. Our results indicate that a) the muon induced upset rate is negligible compared to neutron induced upset rate, and b) the introduction of 3D Tri-Gate transistors reduced the susceptibility to muons by approximately two orders of magnitude relative to 32nm planar cross sections.