Multiplexer based Voltage Controlled Delay Buffer Element
- Resource Type
- Conference
- Authors
- Saxena, Pooja; Khan, Mohd Amir
- Source
- 2019 IEEE 5th International Conference for Convergence in Technology (I2CT) Convergence in Technology (I2CT), 2019 IEEE 5th International Conference for. :1-5 Mar, 2019
- Subject
- Bioengineering
Communication, Networking and Broadcast Technologies
Components, Circuits, Devices and Systems
Computing and Processing
Fields, Waves and Electromagnetics
Nuclear Engineering
Photonics and Electrooptics
Power, Energy and Industry Applications
Robotics and Control Systems
Signal Processing and Analysis
Delays
Voltage control
Logic gates
Multiplexing
Clocks
Capacitors
Delay lines
Time-to-Digital Converter (TDC)
Current Starved Inverter
Delay Lock Loop (DLL)
Process Voltage and Temperature (PVT)
- Language
This paper presents a voltage controlled delay buffer using a 2:1 multiplexer, designed in 0.35 μm CMOS process. The multiplexer is realized with transmission gate, which results in achievement of high speed, low power and full swing output characteristics of delay buffer. The least attained post layout rising edge delay is 120 ps that is comparable with standard cell inverter. The delay regulation range achieved over control voltage of 0 V to 3.3 V is from 120ps to 560ps. The performance of delay buffer for single edge delay control across PVT variations is successfully verified by design of modified delay lock loop.