Learning To Optimize VLSI Design Problems
- Resource Type
- Conference
- Authors
- Jayadeva; Sameena Shah; Suresh Chandra
- Source
- 2006 Annual IEEE India Conference India Conference, 2006 Annual IEEE. :1-4 Sep, 2006
- Subject
- Computing and Processing
Communication, Networking and Broadcast Technologies
General Topics for Engineers
Design optimization
Very large scale integration
Support vector machines
Machine learning
Cost function
Information analysis
Constraint optimization
Analytical models
Circuit simulation
CMOS analog integrated circuits
Optimization
Global optimum
VLSI circuits
Transistor sizing
Analog design automation
- Language
- ISSN
- 2325-940X
2325-9418
We show applications of a new global optimization strategy that combines support vector machine (SVM) learning with simple local search. The use of SVM learning allows prediction of locations of the global optimum from knowledge of a few local minima. This is particularly valuable in VLSI design applications, where the search space is extremely large. The approach does not need the cost function or constraints to be provided in analytical form, thus allowing the optimizer to be linked with a circuit simulator that provides highly accurate information about circuit behavior. Experimental results show that the optimizer is highly effective in sizing transistors in analog CMOS circuits.