The interface trap density $(\boldsymbol{D}_{\text{it}})$ has been recognized as an important parameter in determining the electrical characteristics and reliability of devices with the scaling down. In this work, therefore, we propose a technique for characterization of interface traps in silicon gate-all-around (GAA) nanosheet (NS) MOSFETs. The proposed technique uses a subthreshold current measured in a single device, so it is possible to simply extract $\boldsymbol{D}_{\text{it}}$ in extremely scaled GAA NS MOSFETs. In addition, it is confirmed that the extraction results are independent of the channel length $\boldsymbol{(L_{\text{ch}}=40,90,140\ \text{nm})}$ and width $\boldsymbol{(W_\text{NS} =20,\ 24,\ 26\ \text{nm})}$. It is also confirmed that the results agree analogous to the results extracted through other characterization techniques on the same wafer.